PIC18LF4423-I/ML【PDF 27/54 页】IC PIC MCU FLASH 8KX16 44QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3828

23页 24页 25页 26页 [27页]28页 29页 30页 31页

2009 Microchip Technology Inc.

DS39755C-page 33

PIC18F2423/2523/4423/4523

2.6

A/D Conversions

Figure 2-4 shows the operation of the A/D Converter

after the GO/DONE bit has been set and the

ACQT<2:0> bits are cleared. A conversion is started

after the following instruction to allow entry into Sleep

mode before the conversion begins.

Figure 2-5 shows the operation of the A/D Converter

after the GO/DONE bit has been set, the ACQT<2:0>

bits have been set to ‘010’ and a 4 TAD acquisition time

has been selected before the conversion starts.

Clearing the GO/DONE bit during a conversion will abort

the current conversion. The A/D Result register pair will

NOT be updated with the partially completed A/D

conversion sample. This means, the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

2TCY wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

2.7

Discharge

The discharge phase is used to initialize the value of

the holding capacitor. The array is discharged before

every sample. This feature helps to optimize the unity-

gain amplifier, as the circuit always needs to charge the

capacitor array, rather than charge/discharge based on

previous measure values.

FIGURE 2-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 2-5:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Code should wait at least 3 TAD after

enabling the A/D before beginning an

acquisition and conversion cycle.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8

TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY – TAD

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

b11

b10

On the following cycle:

Discharge

TAD13

TAD12

TAD1

(typically 200 ns)

Set GO/DONE bit

(Holding capacitor is disconnected)

Conversion starts

(Holding capacitor continues

acquiring input)

TACQT Cycles

TAD Cycles

Automatic

Acquisition

Time

b11

b10

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

On the following cycle:

TAD1

Discharge

(typically

200 ns)

Points to end of TACQT period (current black arrow)

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式